Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Many devices, such as micro-processors, or other related devices include onboard memory which contains one or more read only memory (ROM) cells.
ROM circuits are generally composed of memory elements disposed in rows or word lines and columns or bit lines. A particular word in memory is generally addressed by energizing the row or word line corresponding to the desired word while also energizing the columns of bit lines for all of the bits corresponding to the addressed word. The read only memory circuits (ROM) are widely used in Basic Input/Output System (BIOS) type of systems, where the code hard coded in it will be read at the start of some operation. After that it will just be a leaky component in a system. Hence, low-leakage and low-power consumption are major goals of a ROM designing.
There are schemes that can reduce static leakage and dynamic power consumption of bit lines like selectively pre-charge bit lines of a selected column. But the ROM memory cell being very dense still gives rise to cross talks, leakage of load transistors within same column, VDD noise to a sense amplifier, etc. These problems give rise to a limited operating speed with unbalanced latching problems. Since bit lines (BLs) are in close proximity, there is a heavy coupling between adjacent BLs. If a cell in an unselected column is programmed as zero, it will couple to an adjacent BL. If this adjacent BL is needed to be kept high (for bit ‘1’) and is to be sensed, then some margin has to be kept in an unbalanced sense amplifier. The leakage of load resistance is another concern for ROM as memory cells are of minimum length, and hence sub-threshold leakage and its deviation are very high.
There is therefore a need for ROMs that improve operational speed while providing power and leakage benefits.